Selected publications

• Won-Jong Lee, Vason P. Srini and Tack-Don Han,"Adaptive and Scalable Load Balancing Scheme for Sort-Last Parallel Volume Rendering on GPU Clusters", International Workshop on Volume Graphics, 2005, Stony Brook, New York, USA (pdf)
• Won-Jong Lee, Vason P. Srini and Tack-Don Han, "Efficient Volume Visualization on GPU Clusters Using a Combination of Hierarchical Data Structures", IEEE Visualization 2005, Minneapolis, MN, United States (pdf)
• C. Chang, K. Kuusilinna, B. Richards, and R.W. Brodersen, “"Implementation of BEE: a Real-time Large-scale Hardware Emulation Engine",” Proc. FPGA 2003, pp. 91-99, Feb. 2003. (pdf)
• C. Chang, K. Kuusilinna, B. Richards, A. Chen, N. Chan, R. W. Brodersen, B. Nikolić, "Rapid Design and Analysis of Communication Systems Using the BEE Hardware Emulation Environment," Proc. IEEE Rapid System Prototyping Workshop, June 2003. (pdf)
• R. W. Brodersen, J. Wawrzynek, V. P. Srini, A. Vladimirescu, D. Orofino, J. Hwang, C. Chang, B. Richards, K. Camera, H. So, N. Zhou, "Reconfigurable HEC Platform", HECRTF Workshop, Washington DC, June 2003 (pdf)
• V. P. Srini, J. M. Rabaey, "Reconfigurable Clusters of Memory and Processors Architecture for Stream Processing Systems," Proc. HPC Asia, Dec. 2002. (pdf)
• V. P. Srini, J. Thendean, and J. M. Rabey, "Reconfigurable Memory Module in the RAMP System for Stream Processing," Proc. ISCA workshop, 2001. (pdf)
• Roy A. Sutton, Vason P. Srini, Jan M. Rabaey, "A multiprocessor DSP system using PADDI-2", Annual ACM IEEE Design Automation Conference, Proceedings of the 35th annual conference on Design automation - Volume 00, 1998, San Francisco, California, United States, pages 62 - 65 (pdf)
• Darren R. Busing, Vason P. Srini, Georges E. Smine, Mike J. Carlton, and Alvin M. Despain, "The Aquarius IIU System", Proceedings of the First Intl. Conference on Systems Integration, Morristown, New Jersey, April 1990 (pdf)
• T. M. Nguyen, V. P. Srini, A. M. Despain, "A two-tier memory architecture for high-performance multiprocessor systems", International Conference on Supercomputing archive, Proceedings of the 2nd international conference on Supercomputing table of contents, St. Malo, France, 1988, pages 326 - 336, (pdf)
• B. Fagin, Y. N. Patt, V. Srini, A. Despain, "Compiling Prolog into microcode: a case study using the NCR/32-000", International Symposium on Microarchitecture, Proceedings of the 18th annual workshop on Microprogramming, 1985, Pacific Grove, California, United States, pages 79 - 88 (pdf)
• Vason P. Srini, "An Architecture for Extended Abstract Data Flow",ISCA 1981, pages 303-326 (pdf)
• Vason P. Srini, "Iterative realization of multivalued logic systems, Multiple-Valued Logic", Proceedings of the eighth international symposium on Multiple-valued logic, 1978, Rosemont, Illinois, United States, pages 188 - 194 (pdf)